The following disclosure relates to electrical circuits and signal processing.
A conventional edge-triggered flip-flop is an electronic circuit that can be used as a storage element in logic circuit design. A conventional edge-triggered flip-flop can change state at a positive edge (rising edge) and/or at a negative edge (falling edge) of a clock pulse on a control input of the edge-triggered flip-flop.
Types of edge-triggered flip-flops include, for example, S-R flip-flops, J-K flip-flops, and D flip-flops. Edge-triggered flip-flops include inputs and outputs. Inputs include signal inputs, a SET input, a RESET input, and a clock input. The signal inputs (e.g., S, R, J, K and D) are generally referred to as synchronous inputs of a flip-flop as the signal inputs affect the state of the flip-flop only on the triggering edge of a clock pulse. The SET and RESET inputs are generally referred to as asynchronous inputs as the SET and RESET inputs can affect the state of a flip-flop independent of a clock pulse.
Desirable attributes for an edge-triggered flip-flop include a short setup time, a short clock-to-output delay, and a low capacitance for input signals and the clock signal. Setup time is the time required for input data to be stable before the triggering edge of a clock pulse. Clock-to-output delay is the time required for output data of a flip-flop to be valid after the triggering edge of a clock pulse.
Conventional sense-amp based edge-triggered flip-flops generally have a shorter setup time and a lower input capacitance than conventional master-slave edge-triggered flip-flops in a CMOS (complementary metal-oxide semiconductor) implementation. In addition, the area of a conventional sense-amp based edge-triggered flip-flop is generally comparable to that of a conventional master-slave edge-triggered flip-flop in CMOS implementation.
FIG. 1 shows a conventional sense-amp based, edge-triggered flip-flop, referred to herein as flip-flop 100. Flip-flop 100 includes p-type transistors P1–P5, n-type transistors N1–N5, and inverters I1–I4. Flip-flop 100 further includes transistors T1–T8, that are operable to perform a multiplexing function. Transistors T1–T4 are controlled by input signals S0–S1, and transistors T5–T8 are controlled by input signals D0–D1. Signals S0–S1 are select signals and signals D0–D1 are data input signals. Select signal S0 selects data input signal D0 and select signal S1 selects data input signal D1. In operation, during a pre-charge cycle—i.e., when CLK input 102 is low, complementary storage nodes A and B are pre-charged to VDD. After the pre-charge cycle (when CLK input 102 is high), one of complementary storage nodes A and B is pulled low to VSS according to a selected one of data input signals D0–D1 and value of D0–D1. Flip-flop 100 includes a single sense pull-down path (to VSS) through transistor N4. An output of flip-flop 100 is latched at output 104.
The multiplexing function of transistors T1–T8 can be used to implement a scan chain test. Scan chain testing is a widely used testing scheme for detecting faults of a logic circuit design. Scan chain tests are typically run at low speeds as scan chain tests are primarily used to test stuck-at faults. Transistors T1–T8 can be used to switch input data between operation data (e.g., data input signal D0) and scan data (e.g., data input signal D1), for supporting a scan chain test.
The inclusion of scan chain test functionality (through the multiplexing function of transistors T1–T8), however, degrades the speed performance of flip-flop 100. For example, the setup time of flip-flop 100 increases due to additional delay caused by the 2-to-1 multiplexing function of transistors T1–T8. Furthermore, the input capacitance of flip-flop 100 increases due to the additional transistors required to implement the 2-to-1 multiplexer at the input of flip-flop 100.
Conventional sense-amp based edge-triggered flip-flops typically do not have built-in asynchronous SET/RESET functions, which is another desirable attribute for an edge-triggered flip-flop. Built-in refers to external logic or internal logic implemented with the logic design of a flip-flop. External logic is typically used to implement only synchronous SET/RESET functions in conventional sense-amp based edge-triggered flip-flops.